TMS320C31PQA40

Product Summary

The TMS320C31PQA40 is a 32-bit, floating-point processor manufactured in 0.6 μm triple-level-metal CMOS technology. The TMS320C31PQA40’s internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 80 million floating-point operations per second (MFLOPS). The TMS320C31PQA40 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. The TMS320C31PQA40 can perform parallel multiply and ALU operations on integer or floating point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I /O, and a short machine-cycle time. High performance and ease of use are results of these features.

Parametrics

TMS320C31PQA40 absolute maximum ratings: (1)Supply voltage range, VDD:–0.3V to 7V; (2)Input voltage range, VI:–0.3V to 7V; (3)Output voltage range, VO:–0.3V to 7V; (4)Operating case temperature range, TC: PQL (commercial):0℃ to 85℃, PQA (industrial):-40℃ to 125℃; (5)Storage temperature range, Tstg:-55℃ to 150℃.

Features

TMS320C31PQA40 features: (1)32-Bit High-Performance CPU; (2)16- /32-Bit Integer and 32- /40-Bit Floating-Point Operations; (3)32-Bit Instruction Word, 24-Bit Addresses; (4)Two 1K × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks; (5)Boot-Program Loader; (6)Fabricated Using 0.6 μm Enhanced Performance Implanted CMOS(EPIC) Technology by Texas Instruments (TI); (7)132-Pin Plastic Quad Flat Package(PQ Suffix); (8)Eight Extended-Precision Registers; (9)Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs); (10)Two Low-Power Modes; (11)Two- and Three-Operand Instructions; (12)Parallel Arithmetic/Logic Unit (ALU) and Multiplier Execution in a Single Cycle; (13)Block-Repeat Capability; (14)Zero-Overhead Loops With Single-Cycle Branches; (15)Conditional Calls and Returns; (16)Interlocked Instructions for Multiprocessing Support; (17)Bus-Control Registers Configure Strobe-Control Wait-State Generation.

Diagrams