(China (Mainland))
Product Summary
The EPM7064STC44-7 is a programmable logic device. The EPM7064STC44-7 high-density, high-performance PLDs is based on Altera second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7064STC44-7 rovides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. EPM7064STC44-7 device in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.
Parametrics
EPM7064STC44-7 absolute maximum ratings: (1)TSTG Storage temperature No bias –65 150 ℃; (2)TAMB Ambient temperature Under bias –65 135 ℃; (3)TJ Junction temperature Ceramic packages, under bias 150 ℃; (4)PQFP and RQFP packages, under bias 135 ℃; (5)IOUT DC output current, per pin –25 25 mA.
Features
EPM7064STC44-7 features: (1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAXR architecture; (2)5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices ISP circuitry compatible with IEEE Std. 1532; (3)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (4)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (5)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (6)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (7)PCI-compliant devices available.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||||
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 EPM7064STC44-7 |
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IC MAX 7000 CPLD 64 44-TQFP |
Data Sheet |
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EPM7064STC44-7F |
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IC MAX 7000 CPLD 64 44-TQFP |
Data Sheet |
Negotiable |
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EPM7064STC44-7N |
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IC MAX 7000 CPLD 64 44-TQFP |
Data Sheet |
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