(China (Mainland))
Product Summary
The 74F112PC is a Dual JK Negative Edge-Triggered Flip-Flop. The 74F112PC contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs of the 74F112PC can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH.
Parametrics
74F112PC absolute maximum ratings: (1)Storage Temperature: -65 to +150℃; (2)Ambient Temperature under Bias: -55 to +125℃; (3)Junction Temperature under Bias: -55 to +150℃; (4)VCC Pin Potential to Ground Pin: -0.5V to +7.0V; (5)Input Voltage: -0.5V to +7.0V; (6)Input Current: -30 mA to +5.0 mA; (7)Voltage Applied to Output in HIGH State (with VCC = 0V); (8)Standard Output: -0.5V to VCC; (9)3-STATE Output: .0.5V to +5.5V; (10)Current Applied to Output in LOW State (Max): twice the rated IOL (mA).
Features
74F112PC features: (1)contains two independent, high-speed JK flipflops with Direct Set and Clear inputs; (2)Synchronous state changes are initiated by the falling edge of the clock; (3)Triggering occurs at a voltage level of the clock and is not directly related to the transition time; (4)The J and K inputs can change when the clock is in either state without affecting the flip-flop.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||
|---|---|---|---|---|---|---|---|---|---|---|
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 74F112PC |
Fairchild Semiconductor |
Flip Flops Dual J-K Flip-Flop |
Data Sheet |
Negotiable |
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74F112PC_Q |
Fairchild Semiconductor |
Flip Flops Dual J-K Flip-Flop |
Data Sheet |
Negotiable |
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