PALCE16V8H-7JC/5

Product Summary

The PALCE16V8H-7JC/5 is an advanced PAL device built with low-power, high-speed, electricallyerasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The PALCE16V8H-7JC/5 macrocell provides a universal device architecture. The PALCE16V8H-7JC/5 provides zero standby power and high speed. At 30-μA maximum standby current, the device allows battery-powered operation for an extended period. The PALCE16V8H-7JC/5 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices.

Parametrics

PALCE16V8H-7JC/5 absolute maximum ratings: (1)Storage Temperature: -65 to +150℃; (2)Ambient Temperature with Power Applied: -55 to +125℃; (3)Supply Voltage with Respect to Ground: -0.5 V to + 7.0 V; (4)DC Input Voltage: -0.5 V to VCC + 0.5 V; (5)DC Output or I/O Pin Voltage: -0.5 V to VCC + 0.5 V; (6)Static Discharge Voltage: 2001 V; (7)Latchup Current (TA = -40 to +85℃): 100 mA.

Features

PALCE16V8H-7JC/5 features: (1)Pin and function compatible with all 20-pin PAL devices; (2)Electrically erasable CMOS technology provides reconfigurable logic and full testability; (3)High-speed CMOS technology: 5-ns propagation delay for -5 version; 7.5-ns propagation delay for -7 version; (4)Direct plug-in replacement for the PAL16R8 series; (5)Outputs programmable as registered or combinatorial in any combination; (6)Peripheral Component Interconnect (PCI) compliant; (7)Programmable output polarity; (8)Programmable enable/disable control; (9)Preloadable output registers for testability; (10)Automatic register reset on power up; (11)Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages; (12)Extensive third-party software and programmer support; (13)Fully tested for 100% programming and functional yields and high reliability; (14)5-ns version utilizes a split leadframe for improved performance.

Diagrams